One issue with conventional transceivers is power consumption. Many conventional transceivers are implemented using analog building blocks which may include low-noise amplifier (LNAs), mixers, active filters, etc. These analog building blocks necessarily have an inherent bias current which results in excess power consumption. Reducing the bias current in these analog building blocks may compromise performance. There is generally a limit to the level that the bias current can be reduced to, depending on modulation and operating condition requirements which set certain performance requirements of a transceiver.
One conventional technique to reduce power consumption is to cycle the bias current by switching various circuits within the transceiver from an active state to low power or standby state. To minimize power consumption, the on-period or active state time is minimized, however, set-up and disable periods that occur while the circuits transition between states to establish proper operating conditions limit the amount of power saving that can be achieved. Another issue with analog building blocks is that they are becoming more challenging to implement on deep sub-micron process nodes making it desirable to minimize the analog block content as well as minimize the implementation area.
Thus, there are general needs for transceivers that operate with reduced power consumption. There are also general needs for transceivers that minimize analog block content as well as minimize the implementation area for analog blocks.